Welcome to EMVL 2023

International Conference on Embedded Systems and VLSI (EMVL 2023)

August 12-13, 2023, Virtual Conference

Accepted Papers
Comparative Analysis of Simulation Techniques:scan Compression and Internal Scan

Parul Patel1, Arvind Rajawat2 and Pooja Jain3, 1, 2Department of Electronics and Communication, Maulana Azad National Institute of Technology Bhopal, India, 3Automotive and Discrete group STMicroelectronics Private Limited Greater Noida, India


With advancement in technology, the feature size of transistors is shrinking and the transistor count in a circuit design is exponentially increasing. As a result, it is hard to control and observe internal nodes leading to complexity in locating and debugging faults specially for sequential circuits. Design for Testability (DFT) provides a way for fault detection of the circuit under test in less simulation duration with little increase in area. Many techniques are proposed under DFT for pattern simulation. In this paper, we have compared two such pattern simulation techniques namely scan compression and internal scan. The experiment is performed on different benchmark circuits, it is observed the simulation time is significantly reduced with increased coverage and a little area overhead.


DFT, Scan Compression, Internal Scan.

Temperature Sensor With Buffer-chain Based Time-to-digital Converter for Ultra-low Voltage Operation

Kaito NAGAI1 and Kimiyoshi USAMI2, 1Graduate School of Engineering and Science, Shibaura Institute of Technology, Japan, 2Department of Computer Science and Engineering, Shibaura Institute of Technology SIT Research labs. International Research Center for Green Electronics


This paper proposes a Time-to-Digital Converter (TDC) based temperature sensor that aims to operate with an ultra-low voltage electromotive force for IoT applications with energy harvesting. Sub-threshold circuit design was exploited for the operation at ultra-low supply voltage. The proposed circuit uses the characteristics of leakage current for temperature measurement. The virtual ground node in the proposed sensor is charged up by leakage current and the charging time changes with the temperature. To measure the temperature-dependent charging time, we used a buffer-chain based TDC to achieve ultra-low voltage operation. Simulation results demonstrated that the minimum supply voltage for the proposed circuit is 0.15V. The power consumption is 407nW and sensing time is 180ns at 25?. The measurable temperature range is from -40? to 85?. The proposed circuit was designed with Renesas SOTB 65nm process. Simulation evaluation was conducted using HSPICE.


Temperature sensor, ultra-low voltage, Time-to-Digital Converter, Sub-threshold.