International Conference on Embedded Systems and VLSI (EMVL 2023)
August 12-13, 2023, Virtual Conference
Comparative Analysis of Simulation Techniques:scan Compression and Internal Scan
Parul Patel1, Arvind Rajawat2 and Pooja Jain3, 1, 2Department of Electronics and Communication, Maulana Azad National Institute of Technology Bhopal, India, 3Automotive and Discrete group STMicroelectronics Private Limited Greater Noida, India
With advancement in technology, the feature size of transistors is shrinking and the transistor count in a circuit design is exponentially increasing. As a result, it is hard to control and observe internal nodes leading to complexity in locating and debugging faults specially for sequential circuits. Design for Testability (DFT) provides a way for fault detection of the circuit under test in less simulation duration with little increase in area. Many techniques are proposed under DFT for pattern simulation. In this paper, we have compared two such pattern simulation techniques namely scan compression and internal scan. The experiment is performed on different benchmark circuits, it is observed the simulation time is
significantly reduced with increased coverage and a little area overhead.